Speed Electrical/Optical Post-Silicon Engineer
Job in
San Diego, San Diego County, California, 92189, USA
Listed on 2026-08-31
Listing for:
Nutanix
Full Time
position Listed on 2026-08-31
Job specializations:
-
Engineering
Systems Engineer, Test Engineer, Electronics Engineer, Hardware Engineer
Job Description & How to Apply Below
Company:
Qualcomm Technologies, Inc.
Job Area:
Engineering Group, Engineering Group ASICS Engineering General
Summary:
Qualcomm Central Hardware Systems (CHS) is seeking a Senior Lead High-speed Electrical/Optical Post-Silicon Engineer to drive hands-on measurements, validation, and debug of next-generation 224G/448G electrical and optical interconnects. The role spans channel characterization, passive measurements, Ser Des validation, PDN debug, and SW/HLOS-driven system validation.
Key Responsibilities High-speed measurements and channel correlation:
Plan and drive 224G/448G electrical/optical measurements and channel characterization across package, PCB, connector, cable, optical module, and system channels. Analyze S-parameters, loss, impedance, skew, crosstalk, jitter/noise, reflections, eye margin, and link robustness; correlate bench data to simulations and package/board models.
Post-silicon bring-up and system validation:
Lead bring-up, characterization, margining, shmoo, stress, compliance-readiness, and SW/HLOS-level validation across reference boards, optical modules, retimers, active/passive cables, and customer-like platforms. Validate tuning, link training, equalization, calibration, FEC/error counters, and workload traffic patterns.
PDN and cross-functional system debug:
Drive PDN measurement and failure isolation across self-noise, coupling, rail droop/ripple, sequencing, package/board power delivery, SI/PI, optics, firmware, drivers, clocking, thermal, software workloads, and platform integration. Translate ambiguous lab/field signatures into RCA hypotheses and debug plans.
Validation content and automation:
Develop automation, data reduction scripts, dashboards, regression flows, and stress content to reproduce, isolate, and prevent electrical/optical/PDN failures.
Cross-functional leadership:
Work with Ser Des PHY, SIPI/PDN, package, PCB, optics, firmware, software, validation, systems architecture, platform, customer engineering, suppliers, and ecosystem partners to drive closure.
Required Qualifications 8+ years of relevant experience in post-silicon, SI/PI, Ser Des/DDR, optical, package/PCB, or system validation.
Strong fundamentals in high-speed digital design, Ser Des/DDR PHYs, SI/PI, transmission lines, jitter/noise, equalization, channel modeling, and measurement correlation.
Hands-on experience with VNAs, oscilloscopes, BERTs, TDR/TDT, rail probing, spectrum analyzers, optical BER/power test equipment, and precision probing/fixturing.
Experience validating and debugging high-speed links such as DDR, PCIe/CXL, Ethernet, UCIe/chip-to-chip, optical module interfaces, retimers, or similar Ser Des-based interfaces.
Strong PDN/system debug experience, including rail noise/ripple, droop/coupling, sequencing, package/board PDN behavior, and workload-driven power stress.
Preferred Qualifications
Experience with 112G/224G/448G-class Ser Des, PAM4/PAM6/PAM8 signaling, DSP-based Ser Des, optical module host interfaces, and advanced equalization/calibration.
Experience with IEEE Ethernet, DDR, PCIe/CXL, UCIe, or similar high-speed electrical/optical standards and debug methodologies.
Experience with optical/electrical co-validation, module bring-up, optical link debug, electrical-to-optical correlation, retimer/re-driver tuning, and link budget closure.
Experience with package/PCB test vehicles, socketed and solder-down platforms, passive/active measurements, and DOE-based characterization.
Experience driving complex customer, supplier, or platform escalations where root cause spans silicon, package, board, firmware, software, thermal, and system conditions.
Familiarity with Linux, UEFI, HLOS validation, embedded instrumentation, telemetry collection, and stress workloads.
Experience / Impact Accelerate post-silicon bring-up and issue closure for next-generation high-speed electrical and optical interconnects.
Improve confidence in 224G/448G channel, package, PCB, optical, PDN, and system readiness.
Reduce late-stage surprises by connecting measurements, validation content, and design feedback across silicon, package, board, software, and platform teams.
Build reusable validation and debug methods…
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