Senior Principal Engineer Digital ASIC Design​/Manager

Job Category: RF Engineering

Requisition Number: SENIO
003620

• Posted :
  August 5, 2026
• Full-Time

Showing 1 location

Salary Range: $214, annually
(Final offer based on experience, education, skills, and market factors)

Why Kyocera?
With nearly 80,000 employees worldwide, Kyocera is a global leader in advanced ceramic technologies used in aerospace, automotive, medical, and semiconductor industries. Our materials power everything from smartphones to space shuttles — and we’re just getting started.

What Makes Us Stand Out?
We don’t just offer jobs — we offer careers with purpose, stability, and growth. Here’s what you can expect:

• 3 weeks of vacation to start (120 hours/year)
• 10 paid holidays annually
• Competitive pay
• 401(k) with company match
• Medical, dental, and vision insurance
• Life insurance
• Flexible Spending Account (FSA)
• Employee Assistance Program (EAP)

• Paid time off to volunteer

• Onsite gyms, walking tracks, and employee gardens at larger locations
• Long-tenured team (many with 30+ years of service!)
• Inclusive and diverse workforce
• A company philosophy rooted in doing the right thing as a human being

Our Philosophy
Kyocera’s culture is deeply inspired by our founder, Dr. Kazuo Inamori. His values guide our decisions and shape our workplace. Learn more about our guiding principles here:

Exempt:Yes
Safety Sensitive:No
Department:TUBIS
Reports To:Not indicated

Responsible for architecture of digital design. Plan and implement digital infrastructure. Plan, oversee, and execute implementation, verification, emulation, and validation of design. Identify potential high-risk areas and present possible resolutions. Drive methodology process and requirement specification documents. Work with external vendors and internal teams in developing plans for micro-architecture, verification, and emulation of digital modules.

• Lead digital design projects from inception to production for mixed signals ICs.
• Hire and manage full-time employees or contractors to support projects.
• Participate in RFIC design flow by architecting and designing digital control functionality which interfaces to I/O and analog functions.
• Perform RTL design, synthesis, LINT, RDC/CDC, LEC, timing constraint development, static timing analysis for digital control logic, which includes off-chip and on-chip serial bus, interface to analog blocks, clock distribution, AMBA bus, state machine, memories, embedded processor cores (RISC-V), bus arbitration, DMA, registers, IO pads, synchronous, asynchronous access and control functions.
• Perform project resource planning, detailed schedule development, milestone and task tracking
• Oversee PNR and ensure integrity of physical layer design.
• Perform/oversee test plan development, digital verification, coverage analysis, and post silicon lab test.
• Support mixed signal verification of design.
• Perform/oversee scan insertion, MBIST and LBIST.
• Perform any other related duties as required or assigned.

• BS or MS degree in Electrical Engineering with 15 years of industry experience in Digital ASIC design in complex multi-million gate architectures and deep submicron technologies, with majority of products with 1stsilicon success
• Proven technical leadership experience
• Ability to work with cross-functional teams and contractors across geographical boundaries
• Strong verbal, communication and organizational skills
• Ability to improve digital design methodology to deliver high quality ICs on schedule
• Experience with requirements development, design reviews and documentation
• Experience with mixed-signal design methodology
• System level experience with architectural tradeoffs for…