Senior FPGA Design Engineer

• Design and simulate FPGA/modem systems
• Work with Ultrascale+ and Versal platforms
• Develop designs using VHDL and System Verilog
• Implement and work with high-speed Ser Des
• Develop and maintain scripting solutions using Python, Perl, Bash, Tcl, and related tools
• Work with Ethernet, Interlaken, PCIe, SPI, I2C, UART, and other communication interfaces

• 10+ years of experience
• FPGA/modem design
• Experience with Ultrascale+ and Versal
• VHDL and System Verilog
• Design and simulation
• High-speed Ser Des
• Solid scripting skills in Python, Perl, Bash, Tcl, etc.
• Communication interfaces such as Ethernet, Interlaken, PCIe, SPI, I2C, UART, etc.
• Active government clearance (nice to have)
• Software-defined radio/modem design background (nice to have)
• Some Peta Linux background (nice to have)
• RF design background (nice to have)
• Encryption experience (nice to have)

Demonstrates extensive experience in FPGA and modem design, utilizing VHDL and System Verilog for simulation and implementation. Proficient in high-speed Ser Des and various communication interfaces, with strong scripting capabilities in Python, Perl, Bash, and Tcl.

• FPGA/Modem Design
• VHDL
• System Verilog
• High-Speed Ser Des
• Communication Interfaces

• FPGA/Modem Design
• VHDL
• System Verilog
• High-Speed Ser Des
• Python
• Perl
• Bash
• Tcl
• Ethernet
• PCIe

• Active Government Clearance

• Software-Defined Radio
• Peta Linux
• RF Design
• Encryption

• Ultrascale+
• Versal
• Interlaken
• SPI
• I2C
• UART