SoC Clock & Power Management Validation Lead AI Accelerator Platform

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group  ASICS Engineering General

Summary:

Qualcomm’s System Validation & Emulation (SVE) team is part of the central SoC validation organization responsible for ensuring end-to-end silicon quality across pre- and post-silicon phases .This role focuses on content quality and system-level validation enablement , offering deep exposure to Qualcomm SoCs through bare-metal validation content , scalable automation frameworks, and complex system debugs. Engineers in this role work across HW and SW boundaries to develop, validate, and scale system-level test content , ensuring high-quality silicon validation across a wide range of SoC domains.

Excellent Opportunity to work on cutting-edge SoCs across multiple product segments , including:

Premium mobile and flagship platforms

Data centerAI Accelerator platform

Role Overview :

Lead end-to-end validation of clock, power, reset, and power-management architectures for next-generation AI accelerator platforms. Drive pre-silicon and post-silicon validation of Clocking infrastructure, PMIC integration, DVFS, and low-power features across complex multi-die AI systems. Partner closely with Architecture, Design, Verification & Firmware teams to debug and root-cause power, performance, stability, and scalability issues. Define validation methodologies, stress workloads, and automation frameworks to ensure robust operation under demanding AI training and inference scenarios.

Own power subsystem bring-up readiness and delivery of production-quality silicon across all program milestones

An ideal candidate combines expertise in Clocking, DVFS, Power Management, PMIC, Firmware, Silicon Bring-up, and AI/HPC platform validation

Roles & Responsibilitie Own the E2E bare metal framework validation SoC clock and power architectures

Validation planning – understand design changes, visualize standalone and system level test requirements and scenarios

Test plan development – clearly document test strategy and dependencies

Conduct validation strategy and test plan review with all stakeholders – architects, designers, verification engineers, software engineers

Develop scalable device drivers, standalone and system tests using CDebug complex issues both on pre-Si and post-Si platforms, provide debug direction

Review validation platform schematics to ensure post-Si debug support – might have to work with platform design team Automate validation process – development, execution, inference using python, perl, shell

Use lab instruments – multimeter, oscilloscopes , logic analyzer

Efficiently collaborate with teams in different time zones – both internal and external

Minimum Requirements:

Bachelor’s degree in engineering (electronics, computer engineering etc.)5+ years of relevant experience in SoC validation and / or associated areas (SW development, embedded systems etc.)Prior work experience in clock/ power validation

Proficient in C, Python Experienced in using lab instruments – multimeter, oscilloscopes , logic analyzers

Exposure to debug tools (JTAG etc.). Knowledge of debug methodology of ARM based So Cs Very  good at problem solving - analytical and debugging skills

Preferred Qualifications:

Prior exposure to below SW skills would add an edge above other applicants:

Experience with Cross-Compilers, Linkers and makefiles

Understanding of coherency and concurrency in modern SoC architecture

Knowledge of PMIC/ prior experience in validating rail power (power measurement tools/ setups)
Knowledge of pre-Silicon validation and debug on FPGA based emulation platforms is a plus Knowledge of RTL and HDLs (Verilog/ System Verilog) would be an additional advantage

Should have prior work experience in a cross functional matrix…