Sr. GPU Engineer – Shader System RTL Design​/Microarchitecture

Category

Chip Design

San Diego, CA

More than 4 Years Work Expe.

About the Team:
With Media Tek’s leadership in SoC design, the Media Tek GPU IP team is committed to developing industry‑leading, feature‑rich, and highly PPA‑competitive graphics IP. Our GPU technology is deployed across flagship and mainstream mobile SoCs and is also a foundational technology for adjacent markets including laptops, IoT, AI, VR/AR, automotive, and custom ASIC applications.

The team is expanding and hiring top GPU talent across multiple disciplines, including architecture, microarchitecture, RTL design, software drivers, compiler technology, performance modeling, power optimization, and silicon validation. Positions are available in our San Diego and San Jose offices.

Position Overview:

We are seeking a Staff / Senior Staff GPU Engineer specializing in Shader System RTL Design and Microarchitecture to help define, design, and deliver next‑generation GPU IP. The ideal candidate will have strong hands‑on experience in GPU shader subsystem microarchitecture, RTL implementation, performance analysis, functional debug, and PPA optimization.

In this role, you will drive the design and optimization of GPU shader systems, including shader core pipelines, thread/warp/wave scheduling, instruction dispatch and issue, execution pipelines, register files, operand collection, scoreboard and dependency management, load/store interaction, cache/memory interfaces, synchronization, and cluster‑level integration. You will collaborate closely with architecture, compiler, software driver, performance modeling, verification, physical design, and post‑silicon teams to deliver best‑in‑class GPU IP for mobile, automotive, laptop, IoT, AI, VR/AR, and ASIC markets.

• Define, develop, and own GPU shader system microarchitecture specifications for industry‑leading graphics and compute IP.
• Lead RTL design and microarchitecture development for shader‑related blocks, including shader core pipelines, thread dispatch, warp/wavefront scheduling, instruction issue, operand collection, register file access, scoreboard, dependency tracking, execution control, and pipeline flow control.
• Design and optimize GPU execution resources, including SIMD/SIMT pipelines, scalar/vector execution units, special function units, load/store interfaces, synchronization mechanisms, barrier handling, and shader control logic.
• Drive shader subsystem integration with GPU front‑end, geometry/tiler, raster, texture, cache, memory subsystem, command processor, firmware, and render backend blocks.
• Collaborate with GPU architecture and compiler teams to translate ISA behavior, API requirements, shader workload characteristics, and performance targets into efficient hardware specifications.
• Work closely with RTL, verification, performance modeling, physical design, software driver, compiler, and post‑silicon teams to identify and resolve architectural, microarchitectural, implementation, timing, and power bottlenecks.
• Analyze GPU workloads and performance data to optimize shader occupancy, instruction throughput, latency hiding, register pressure, cache locality, memory bandwidth efficiency, workload balancing, and power efficiency.
• Drive PPA optimization across shader subsystem design, balancing power, performance, area, timing, frequency, utilization, and implementation complexity.
• Contribute to full GPU IP development lifecycle, including microarchitecture definition, RTL coding, lint/CDC/RDC cleanup, functional verification support, synthesis, timing closure, tape‑out, bring‑up, and post‑silicon debug.
• Debug and resolve complex pre‑silicon and post‑silicon issues related to shader functionality, performance, power, timing, and area.
• Develop and review high‑quality System Verilog RTL and microarchitecture documentation with strong emphasis on correctness, scalability, reuse, and maintainability.
• Partner with verification teams to define test plans, coverage goals, assertions, debug strategies, and directed/random test scenarios for shader subsystem validation.
• Influence future GPU architecture directions through technical analysis,…