Digital Architect

# Digital Architect Snowcap's superconducting digital chips operate under physical constraints with no CMOS equivalent — pulse-based logic, extreme fan-out limits, and a timing model built from the ground up. The architectural assumptions embedded in every modern chip design don't apply here. You will define how the system works — top to bottom — and write the specification that every downstream design, verification, and test decision is anchored to.

Team Chip Architecture Employment Full -time

Posted

May 2026

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01

About the Role Snowcap is building a large-scale digital compute system on superconducting PCL logic. The architecture for that system does not exist anywhere — not in textbooks, not in prior product, not at any other company. CMOS reference designs do not transfer cleanly because the logic family, clocking, interconnect, and energy model are all different from the ground up. This role owns the architecture from the top.  

You will define the top-level chip architecture: system partitioning, clocking strategy, interconnect hierarchy, I/O, and the test strategy that flows out of those choices. You will work directly with physics leads to translate Josephson junction and PCL device constraints into architectural requirements, and you will hand a clean microarchitecture specification to the Digital Microarchitect. We are a flat, matrixed organization — there is no architecture committee, no review board between you and the decision.  

In twelve months, the architecture document you produce should be the single source the rest of the chip team — RTL, verification, physical design, test — reasons from. It should be defensible against physics, buildable in the fab capability we have, and testable with the lab we are standing up. That is the bar.
02

What You'll Own
- Own the top-level architecture specification for Snowcap's PCL digital chips — system partitioning, block hierarchy, and the document the rest of the team builds from.  - Define the clocking strategy for a non-CMOS logic family where conventional synchronous design assumptions do not apply.  - Design the on-chip interconnect hierarchy and I/O architecture, including the cryogenic-to-room-temperature boundary that no CMOS reference design has to think about.  

- Establish the chip's test strategy and test protocol at the architectural level — what is observable, what is controllable, what gets verified where, and what the lab has to be able to measure.  - Partner with physics leads to translate Josephson junction and PCL device behavior into architectural constraints and budgets — and push back when an architectural choice asks more from the device than the physics will deliver.  

- Drive the architecture-to-microarchitecture handoff: produce the specification, defend it under review, and revise it when downstream work surfaces a real problem.  - Make the compute/memory/interconnect tradeoffs that determine what workloads this system is good at — with AI inference and HPC-class workloads as the primary lens.  - Set the standards for what an architecture specification at Snowcap looks like — clarity, completeness, and the kind of rigor that downstream RTL, verification, and test engineers can actually rely on.03

What We Need to See
- Lead or principal architect on a production digital chip program — CPU, GPU, TPU, NPU, or similar — where your architectural decisions shipped in silicon that real workloads ran on.  - Demonstrated ability to reason from first-principles device physics constraints up to system-level architecture. PCL design space requires this; conventional CMOS architects who treat the device as a fixed primitive will not be effective here.  

- Track record of writing the architecture…