SOC Verification Engineer

** Weekly

Hours:

** 40

** Role Number:*
* ** Summary*
* Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.

The SOC Verification Engineer will be responsible for pre-silicon RTL verification of block and top level SOC. With deep understanding of SOC architecture and meticulous attention to details, you will interact with all disciplines to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.

** Description*
* Understand details of microarchitecture and build block / chip level testbench using best-in-class verification methodology.
Create verification plan from specification and in coordination with architects.
Generate directed and ingenuous constrained random tests.
Create/analyze coverage model and enhance testbench/test to increase coverage.
Build automated flows for block and chip level verification.
Debug failures, manage bug tracking, and close coverage.
Hold detailed verification reviews and set standard for coding quality.
Work closely with team members to improve methodology and flow.

** Minimum Qualifications*
* + Solid fundamentals in Verilog and System Verilog for verification.

+ Basic knowledge of UVM methodology.

+ Solid verification skills in problem solving and debugging.

+

Experience with Constrained Random testing is a plus.

+ Good understanding of overall verification flow

+ Knowledge of industry standard interfaces like I2C, UART, SPI.

+ Understanding and usage of System Verilog Assertion (SVA)

+ Programing experience in C

+ Experience writing scripts in languages such as Perl or Python a plus.

+ Should be a great teammate with excellent communication skills and the desire to take on diverse challenges.

** Preferred Qualifications*
* + Typically requires MSEE with 0-3+ years of experience

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