DFT Engineer

Title:

Lead/ Principal / DMTS – SoC DFT Architect

Location:

San Jose, Bay Area | 5 days onsite

Employment Type:

Full-Time

At Eximeitas Design
, we are looking for a hands‑on technical leader to own full‑chip (SoC) DFT architecture and signoff for advanced silicon programs.

This is not a flow‑execution role. We are seeking someone who drives strategy, architecture, insertion, and cross‑functional alignment from RTL through silicon.

• Full‑chip SoC DFT architecture & methodology
• Early RTL DFT insertion & validation
• Scan / MBIST insertion & signoff
• ICL / PDL development and IJTAG integration
• SSN‑aware DFT planning
• DFT‑mode STA (shift/capture timing, constraints, cross‑domain handling)
• Cross‑functional collaboration with RTL, PD, STA, and Physical teams

• Proven experience leading at least one full SoC DFT implementation
• Deep expertise with Tessent / Siemens / Mentor tool suite
• Strong understanding of compression, power‑aware test, and clocking strategy
• Ability to drive reviews, signoff, and technical decisions

If you’ve architected DFT at the SoC level and want to build high‑quality silicon with real influence, we should talk.

Reach out or refer:
Mohini.tyagiign