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Senior Hardware Design Engineer, Devices

Job in San Francisco, San Francisco County, California, 94199, USA
Listing for: HP IQ
Full Time position
Listed on 2026-02-24
Job specializations:
  • Engineering
    Systems Engineer, Hardware Engineer
  • IT/Tech
    Systems Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 120000 - 165000 USD Yearly USD 120000.00 165000.00 YEAR
Job Description & How to Apply Below

Overview

HP IQ is HP’s new AI innovation lab. Combining startup agility with HP’s global scale, we’re building intelligent technologies that redefine how the world works, creates, and collaborates. We’re assembling a diverse, world-class team—engineers, designers, researchers, and product minds—focused on creating an intelligent ecosystem across HP’s portfolio. Together, we’re developing intuitive, adaptive solutions that spark creativity, boost productivity, and make collaboration seamless.

We create breakthrough solutions that make complex tasks feel effortless, teamwork more natural, and ideas more impactful—always with a human-centric mindset. By embedding AI advancements into every HP product and service, we’re expanding what’s possible for individuals, organisations, and the future of work. Join us as we reinvent work, so people everywhere can do their best work.

About

The Role

HP IQ is seeking a Senior Hardware Design Engineer to support the design and development of low-power electronic devices. This role focuses on detailed schematic execution, validation, and debugging under the technical direction of senior engineers. The ideal candidate has strong circuit fundamentals, hands-on experience with schematic and layout tools, and a background working within well-defined engineering processes at top-tier organizations.

What

You Might Do
  • Power architecture responsibility for a wearable device covering SoC states, sensor, audio, and memory architecture tradeoffs at board level.
  • Battery, PCM, and charging profile definition and validation
  • Design power experiments, test plans, and measurement & telemetry mechanisms across firmware and hardware to optimize power and performance.
  • Build and maintain system-level power models to model expected power consumption for user profiles. Map power models by subsystem, correlating modeled behavior with instrumented measurements.
  • Define user profiles, power and sleep states, and low-power operating modes
  • Partner closely with product, hardware, firmware, manufacturing, and regression QA to drive alignment and execution toward power targets.
Essential Qualifications
  • Bachelors or Masters of Science degree in Electrical Engineering, Computer Science, or Physics, or a related field; advanced degree preferred.
  • 5+ years of professional experience in electrical engineering and system architecture.
  • Strong understanding of circuit fundamentals, including low-power analog and high-speed signaling.
  • Hands-on experience with Cadence schematic capture and PCB layout tools.
  • Proven experience executing schematic design, validation, and debugging.
  • Ability to work effectively under technical direction and within cross-functional team.
Preferred Skills
  • Experience leading or contributing to low-power consumer or medical electronic systems from concept through production.
  • Background at top-tier organizations with proven, mature hardware development practices.
  • Experience with small, space-constrained devices and power-sensitive designs.
  • Strong problem-solving skills with the ability to debug complex hardware issues efficiently.
Salary & Benefits

Salary Range: $120,000 - $165,000

The salary range for this role is listed above. Final salary offered is based upon multiple factors including individual job-related qualifications, education, experience, knowledge and skills.

Compensation & Benefits (Full-Time Employees):

  • Health insurance
  • Dental insurance
  • Vision insurance
  • Long term/short term disability insurance
  • Employee assistance program
  • Flexible spending account
  • Life insurance
  • Generous time off policies, including:
    • 4-12 weeks fully paid parental leave based on tenure
    • 11 paid holidays
    • Additional flexible paid vacation and sick leave (US benefits overview)
Why HP IQ?

HP IQ is HP’s new AI innovation lab, building the intelligence to empower humanity—reimagining how we work, create, and connect to shape the future of work.

  • Innovative Work – Help shape the future of intelligent computing and workplace transformation.
  • Autonomy and Agility – Work with the speed and focus of a startup, backed by HP’s scale.
  • Meaningful Impact – Build AI-powered solutions that help people and organisations thrive.
  • Flexible Work Environment –…
Position Requirements
10+ Years work experience
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