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Senior IP Physical Design Lead — RTL to GDSII

Job in San Francisco, San Francisco County, California, 94199, USA
Listing for: Eliyan
Full Time position
Listed on 2026-02-28
Job specializations:
  • Engineering
    Systems Engineer, Engineering Design & Technologists
Salary/Wage Range or Industry Benchmark: 60000 - 80000 USD Yearly USD 60000.00 80000.00 YEAR
Job Description & How to Apply Below
A leading chiplet startup in San Francisco is seeking a Sr Staff / Principal Physical Design Engineer to innovate and drive the development of cutting-edge ASICs.

This role offers the opportunity to oversee the entire design flow from RTL to GDSII while working with a team of experts. Candidates should have a strong background in physical design, timing closure, and mixed signal integration. Excellent communication and leadership skills are essential for ensuring alignment across engineering teams and successful project execution.
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Position Requirements
10+ Years work experience
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