Analog Layout Engineer
Job in
San Francisco, San Francisco County, California, 94103, USA
Listed on 2026-06-01
Listing for:
Capgemini
Full Time
position Listed on 2026-06-01
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Electrical Engineering
Job Description & How to Apply Below
Choosing Capgemini means choosing a company where you will be empowered to shape your career in the way you'd like, where you'll be supported and inspired by a collaborative community of colleagues around the world, and where you'll be able to reimagine what's possible. Join us and help the world's leading organizations unlock the value of technology and build a more sustainable, more inclusive world.
** About the job you are considering*
* We are seeking an experienced Analog / RF Layout Designer to provide onsite support for advanced semiconductor nodes while partnering with a highly collaborative, global design and layout organization. In this role, you will contribute to cutting-edge analog and mixed-signal IP development, working across complex technologies such as FinFET and deep sub-micron processes. This is an excellent opportunity for a hands-on layout expert who thrives in technically challenging environments and enjoys end-to-end ownership from block-level design through top-level integration.
** Your role*
* + Independently develop
** block‑level and IP‑level analog/RF layouts** , partnering closely with circuit designers and global layout teams to drive designs from concept to tape‑out.
+ Own
** floor planning, placement, routing, and optimization
** for complex analog and mixed‑signal blocks, including
** Ser Des, ADC/DACs, PLLs, and related IPs** .
+ Lead and support
** top‑level integration
** of multiple analog and mixed‑signal blocks within larger SoCs.
+ Apply deep expertise in
** advanced deep sub‑micron and FinFET process technologies** , incorporating fabrication, EM, ESD, latch‑up, and reliability considerations into layouts.
+ Resolve complex
** DRC, LVS, antenna, and verification issues** , exercising strong technical judgment while collaborating across geographies and mentoring or guiding team members as a technical lead.
** Your skills and experience*
* + Bachelor's degree in Electrical Engineering, Electronics, or a related field.
+ 6+ years of hands-on experience in analog and/or RF layout design (8+ years preferred).
+ Proven experience with analog floor planning and layout for complex modules such as Ser Des, ADC/DAC, PLLs, and similar high-speed or precision circuits.
+ Strong understanding of analog layout best practices for deep sub-micron CMOS and FinFET technologies.
The base compensation range for this role in the posted location is: $97,700 to $ 203,800 per year.
Capgemini provides compensation range information in accordance with applicable national, state, provincial, and local pay transparency laws. The base compensation range listed for this position reflects the minimum and maximum target compensation Capgemini, in good faith, believes it may pay for the role at the time of this posting. This range may be subject to change as permitted by law.
The actual compensation offered to any candidate may fall outside of the posted range and will be determined based on multiple factors legally permitted in the applicable jurisdiction.
These may include, but are not limited to:
Geographic location, Education and qualifications, Certifications and licenses, Relevant experience and skills, Seniority and performance, Market and business consideration, Internal pay equity.
It is not typical for candidates to be hired at or near the top of the posted compensation range.
In addition to base salary, this role may be eligible for additional compensation such as variable incentives, bonuses, or commissions, depending on the position and applicable laws.
** Capgemini offers a comprehensive, non-negotiable benefits package to all regular, full-time employees.
** In the U.S. and Canada, available benefits are determined by local policy and eligibility and may include:
+ Paid time off based on employee grade (A-F), defined by policy:
Vacation: 12-25 days, depending on grade, Company paid holidays, Personal Days, Sick Leave
+ Medical, dental, and vision coverage (or provincial healthcare coordination in Canada)
+ Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada)
+ Life and disability insurance
+ Employee assistance programs
+ Other benefits as provided by…
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