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Principal Digital Design Engineer
Job in
San Francisco, San Francisco County, California, 94199, USA
Listed on 2026-06-02
Listing for:
Astera Labs
Full Time
position Listed on 2026-06-02
Job specializations:
-
Engineering
Systems Engineer, Hardware Engineer
Job Description & How to Apply Below
Requirements
- The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ethernet, Infiniband, DDR, NVMe, USB, etc ,
- Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred ,
- +8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications ,
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision ,
- Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! ,
- Authorized to work in the US and start immediately ,
- Hands-on, thorough knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc ,
- Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc ,
- Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production ,
- Experience with Synopsys and/or Cadence digital design tools/flows ,
- Good knowledge of design for test (DFT), stuck-at and transition scan test insertion ,
- Familiarity with UVM based design verification ,
- Silicon bring-up and debug expertise ,
- Small-geometry CMOS (≤28nm) design ,
- (Desirable) Firmware development with C-language, scripting with Python or other equivalent programming languages ,
- (Desirable) Development/support for PCIe or Ethernet Switch products
- We are looking for Principal Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers.
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