SIPI Architect -Speed SerDes

Position: SIPI Architect for High-Speed SerDes
** Role Number:*
* ** Summary*
* In this position, you will work with the team that develops SoCs. In this high-impact role, you will define and own the end-to-end signal and power integrity strategy for cutting-edge high speed Ser Des. You will be responsible for ensuring robust interconnect performance from silicon to system. This position requires deep expertise in leading-edge Ser Des technologies (224G+), modern interconnect protocols, and system-level co-design.

** Description*
* As the SIPI Architect, you will define and own the end-to-end signal and power integrity architecture for high-speed Ser Des interconnects. You will guide technical direction across various teams, lead system-level trade-off analyses, and ensure design robustness through advanced modeling and validation.

** Minimum Qualifications*
* + BS and 10 +years of relevant industry experience.

** Preferred Qualifications*
* + MS or PhD in Electrical Engineering or a related field with 10+ years of relevant industry experience.

+ Deep expertise in system-level SIPI for high-speed Ser Des (112G/224G and beyond).

+ Proven experience architecting solutions for high-performance interconnects using standards such as Ethernet, PCIe, UAL and CXL.

+ Expert in end-to-end channel modeling and link budget analysis, including statistical (e.g., COM) and time-domain simulation.

+ In depth understanding of Ser Des TX/RX equalization techniques, clocking and power delivery trade-offs.

+ Experience leading cross-functional teams and driving technical consensus across silicon architecture, circuit design, packaging and system hardware groups.

+ Experience designing interconnects for large-scale systems such as those in data center or high-performance computing (HPC) environments.

+ Familiarity with emerging interconnect technologies, including co-packaged optics (CPO), and advanced packaging (e.g., 2.5D/3D integration).

+ Familiarity with system-level power integrity (PDN) and thermal co-design for large-scale, high-power ASICs.

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