PD Engineer

* Experience : 8+

* Block-level physical implementation from RTL to GDSII, focusing on timing, power, and area (PPA) optimization for high-speed Ser Des and interconnect subsystems.

* Architect implementation strategies for high performance RISC-V cores, supporting complex clock/power domains and floor plans.

* Collaborate with RTL, STA, and verification teams to ensure timing and physical convergence.

* Own advanced physical design tasks including:

* EM/IR and power grid optimization for high-current blocks

* Congestion mitigation and routing-aware floor planning

* RC-aware timing closure across corners and PVTs

* Clock tree synthesis and skew management across domains .

* Drive signoff closure: DRC, LVS, antenna, ERC, and tapeout readiness using industry-standard tools (e.g., Innovus, ICC2, Calibre, Voltus, Red Hawk).

* Contribute to and improve physical design automation infrastructure using Tcl, Python, Perl, and other scripting tools.