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Cellular ASIC Protocols Architect & RTL Expert

Job in San Francisco, San Francisco County, California, 94199, USA
Listing for: Apple Inc.
Full Time position
Listed on 2026-06-04
Job specializations:
  • Engineering
    Systems Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 100000 - 125000 USD Yearly USD 100000.00 125000.00 YEAR
Job Description & How to Apply Below
A leading technology company in San Francisco is looking for a Cellular ASIC Design Engineer to architect and implement protocol processing hardware for wireless SoCs. The candidate should have over 10 years of relevant experience and strong skills in System Verilog and Verilog. Responsibilities include hardware implementation, optimization of architectures, and debugging in the lab. The position offers a comprehensive compensation package with competitive base pay, stock options, and extensive employee benefits.
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