RTL Design Engineer
Job in
San Francisco, San Francisco County, California, 94199, USA
Listed on 2026-06-12
Listing for:
Oho Group
Full Time
position Listed on 2026-06-12
Job specializations:
-
Engineering
Systems Engineer, Hardware Engineer, Electronics Engineer
Job Description & How to Apply Below
Seeking a Senior RTL Design Engineer to lead frontend silicon design for next-generation AI acceleration systems.
Responsibilities- Develop and optimize RTL for AI centric hardware subsystems
- Implement micro-architectures focused on datapaths, memory, and performance
- Drive PPA optimization across frequency, power, and area targets
- Lead synthesis, timing closure, and frontend verification
- Collaborate with architecture teams on HW/SW co-optimization for AI workloads
- 5+ years in silicon/ASIC frontend design
- Strong RTL expertise in Verilog/System Verilog
- Experience with synthesis, timing analysis, verification, and power optimization
- Deep understanding of PPA trade-offs and memory bandwidth optimization (SRAM)
- Proficiency with EDA tools including Verilator, Yosys, and OpenSTA
- AI accelerator or NPU design experience
- ML-for-EDA or AI-assisted hardware optimization background
- Edge AI or automotive safety familiarity
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