Director, Hardware Engineering; Physical Design

SBT is the exclusive executive recruiting firm for this confidential position.

This confidential client is strategically bringing on a Director of Hardware Engineering (Physical Design) to build and lead the company’s engineering organization from the ground up. This is a technical, hands‑on leadership role focused on driving physical implementation and full‑chip execution across complex SoCs, while also contributing to broader chip architecture, front‑end design collaboration, and overall silicon development strategy.

The Director will define and scale best‑in‑class implementation methodologies, partner closely with RTL, architecture, verification, packaging, and systems teams, and help shape the long‑term roadmap for advanced silicon programs. This individual will serve as both a technical leader and organizational builder, guiding cross‑functional execution from architectural definition through tapeout and productization.

• Lead end‑to‑end physical implementation for complex SoCs, including synthesis, floor planning, power planning, clock/reset architecture, place‑and‑route, timing closure, physical verification, and final tapeout across advanced process nodes.
• Build, scale, and mentor a high‑performing Hardware/Physical Design organization, establishing implementation methodologies, PD workflows, automation strategies, and best practices for high‑performance silicon development.
• Partner closely with architecture, RTL, verification, DFT, packaging, and systems engineering teams to influence microarchitecture, physical‑aware RTL development, timing/power tradeoffs, and overall chip integration strategy from early design through production readiness.
• Drive top‑level execution and technical strategy for large‑scale multi‑IP SoC programs, optimizing PPA, power delivery, routability, signal integrity, and manufacturability while contributing to broader hardware engineering direction and long‑term silicon roadmap planning.

• Significant industry experience in Physical Design engineering with expertise in full‑chip implementation, advanced‑node SoCs, timing closure, physical verification, and tapeout signoff.
• Strong hands‑on experience leading large‑scale implementation efforts across floor planning, clock/power distribution, place‑and‑route, and PPA optimization.
• Proven ability to collaborate with architecture, RTL, verification, DFT, packaging, and systems teams in physically aware chip development environments.
• Demonstrated success building, mentoring, and scaling high‑performing Physical Design or Hardware Engineering teams and methodologies.
• Experience with high‑performance compute, AI/ML, networking, DSP, or other compute‑intensive architectures, along with modern EDA tools and automation flows.