Principal Technical Program Manager - DSP​/Mixed-Signal ASIC Development - TeraWave

Application close date:

Applications will be accepted on an ongoing basis until the requisition is closed.

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We're working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight!

Blue Origin is pioneering the future of space-based communications with Tera Wave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide.

Role Overview

Blue Origin seeks a program manager to lead development of the advanced mixed-signal/DSP ASIC, including Digital Beamforming (DBF). These high-performance SoCs play a critical role at the core of Tera Wave's satellite communication system. This role spans architecture definition through tapeout, bring-up, and production. The candidate will coordinate across design, verification, physical implementation, IP integration, validation, and production teams to deliver SOCs managing multiple signal chains from bits to antennas including SERDES, and high-speed ADC/DAC interfaces within aggressive power and schedule targets.

Key Responsibilities:

* Drive end-to-end MS/DSP SoC development from architecture freeze through production, including IP selection, design services management, and foundry engagement.

* Build and maintain integrated schedules across internal and external covering architecture definition, IP procurement, RTL design, verification, physical implementation, and tapeout.

* Coordinate resolution of critical open architecture trades on the overall signal chain including hybrid vs. full digital beamforming, SERDES, IF sampling strategy, ADC/DAC analog interface configuration, and element count.

* Track and mitigate technical risks related to power budget, IP maturity (non-silicon-proven DAC), NDA/legal pipelines, and IT/CAD infrastructure readiness

* Align overall DSP requirements including digital beamforming specifications and analog/digital interface definitions between FEIC, Modem, and system-level teams to ensure coherent operation across the full phased-array signal chain

* Manage design services partners and IP vendors including SOW execution, milestone reviews, and technical accountability.

* Monitor critical path milestones through tapeout and first silicon bring-up, maintaining schedule confidence through proactive risk management.

* Support power, area, and cost optimization trades in collaboration with design and systems engineering teams

* Oversee the post-silicon development phases including bring-up, bench-validation, characterization, qualification and production ramp.

Basic Qualifications:

* Bachelor's degree in Electrical or Computer Engineering

* 10+ years in technical program management or semiconductor development, with direct mixed-signal/DSP ASIC/SoC ownership

* 5+ years leading complex digital SoC programs from architecture definition through tapeout on advanced process nodes (7 nm or below)

* Experience managing external design services vendors and IP licensing agreements across multi-party programs

* Demonstrated expertise in program planning, critical-path scheduling, and technical risk management for multi-disciplinary ASIC programs

Preferred Qualifications:

* Advanced degree in Electrical Engineering, Computer Engineering, or a related field

* Hands-on experience with high-speed SERDES integration or high-sample-rate ADC/DAC interfaces

* Proficiency with digital beamforming architectures and signal-processing pipeline design for phased-array antenna systems

* Experience in satellite, aerospace, or space-grade ASIC programs requiring radiation/reliability features

* Knowledge of advanced-node design flows and engagement models with approved design services providers

Base Pay Range for:

CA applicants is $ - $

Other site ranges may…