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SVP of Engineering; SoC​/ASIC Design

Job in San Francisco, San Francisco County, California, 94199, USA
Listing for: SBT
Full Time position
Listed on 2026-06-14
Job specializations:
  • Engineering
    Systems Engineer, Electrical Engineering, Electronics Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 125000 - 150000 USD Yearly USD 125000.00 150000.00 YEAR
Job Description & How to Apply Below
Position: SVP of Engineering (SoC/ASIC Design)

SBT is the exclusive executive recruiting firm for this confidential position.

This confidential startup company is developing advanced semiconductor technologies focused on high-performance connectivity and next-generation infrastructure applications. Backed by experienced technical leadership and strong market momentum, the organization is rapidly scaling its engineering operations as it advances toward major product and silicon milestones.

Role
  • Lead and scale a multi-disciplinary semiconductor engineering organization spanning analog, mixed-signal, RTL, physical design, CAD, and layout teams, driving execution from architecture through tape-out and silicon validation.
  • Serve as the operational engineering leader for the organization, establishing engineering processes, program reviews, schedule accountability, risk management, and cross-functional coordination to ensure successful delivery across multiple concurrent chip programs.
  • Provide technical leadership across high-speed analog and mixed-signal development efforts, supporting complex SoC and ASIC design initiatives in a fast-paced engineering environment.
  • Partner closely with executive leadership and CTO/founder-level technical visionaries to translate long-term product strategy into executable engineering roadmaps, scalable organizational structures, and measurable development milestones.
  • Drive seamless collaboration across analog, RTL, DFT, verification, implementation, layout, and lab validation teams, ensuring efficient integration, production readiness, and successful post-silicon bring-up.
  • Build and mentor a world-class engineering organization by recruiting, developing, and leading senior engineering talent while helping evolve the company from an organically grown startup structure into a scalable, high-performance engineering organization.
Qualifications
  • 15+ years of semiconductor engineering experience with significant leadership responsibility across analog, mixed-signal, RTL, and physical implementation organizations.
  • Proven track record leading complex SoC or ASIC development programs from architecture and design through tape-out, silicon bring-up, validation, and production.
  • Strong technical expertise in high-speed analog and mixed-signal semiconductor technologies, with experience supporting advanced ASIC or connectivity-focused development efforts.
  • Demonstrated success building, scaling, and managing cross-functional engineering organizations, including analog design, RTL, verification, CAD, physical design, and layout teams.
  • Strong operational leadership skills with experience driving engineering execution, program management, schedule accountability, resource planning, and organizational process improvement in fast-paced environments.
  • Experience working within high-growth semiconductor or infrastructure technology companies, with the ability to balance technical credibility and executive-level engineering leadership.

On-site location preferences based on qualifications

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