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CPU Design Verification Engineer — UVM Specialist
Job in
San Francisco, San Francisco County, California, 94199, USA
Listed on 2026-06-14
Listing for:
ALTEN Group
Full Time
position Listed on 2026-06-14
Job specializations:
-
Engineering
Test Engineer, Electronics Engineer
Job Description & How to Apply Below
ALTEN Group is seeking a Design Verification Engineer in San Francisco to develop and maintain UVM-based verification environments. The role includes verifying CPU subsystems and implementing constrained-random testing.
The ideal candidate will have over 5 years of Design Verification experience with strong skills in System Verilog and UVM. Familiarity with Instruction Set Simulators and experience with random instruction generators are preferred.
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