Senior Design Verification Engineer

Requirements

• BS in Electrical Engineering, Computer Science or related field with 12 + years of Industry experience or MS Electrical Engineering, Computer Science or related field preferred with 7 + years industry experience
• Experience in SoC verification cycle from architecture to tape out to bring up
• Good knowledge of verification methodologies such as UVM/OVM etc
• Hands on ASIC-SoC Design verification tests and debug experience
• Fluency with System Verilog randomization constraints, coverage, and assertions methodology
• Good problem-solving skills, and the passion to take on challenges (particularly in AI domain)
• Good experience with System Verilog, and verification methodology (UVM/OVM/VMM)
• Passionate about AI and thriving in a fast-paced and dynamic startup culture
• (Desirable) Experience with C/C++, SystemC (a big plus!)
• (Desirable) Successfully lead creation/implementation of multiple SoC verification environments and tape out efforts

• We want to build a company and a culture that sustains the tests of time
• We offer the candidate a very unique opportunity to express themselves and become a future leader in an industry that will have a huge influence globally
• We are striving to build a culture of transparency, inclusiveness and intellectual honesty while ensuring all our team members are always learning and having fun on the journey
• We have built the industry’s first highly programmable in-memory computing architecture that applies to a broad class of applications from cloud to edge
• The candidate will get to work on a path breaking architecture with a highly experienced team that knows what it takes to build a successful business