Senior Memory Circuit Design Engineer - DDR/DDR5 & MRAM
Job in
San Francisco, San Francisco County, California, 94199, USA
Listed on 2026-07-20
Listing for:
Gyga Force
Full Time
position Listed on 2026-07-20
Job specializations:
-
Engineering
Electronics Engineer, Hardware Engineer, Test Engineer, Systems Engineer
Job Description & How to Apply Below
Gyga Force is seeking a Senior or Principal Memory Circuit Design Engineer in San Francisco to lead architecture, design, and optimization of high-speed DDR4/DDR5 interfaces for next-generation MRAM products. You will collaborate with architecture, memory, verification, and product teams to ensure robust, high-performance subsystems.
The role reports to the VP of Engineering and offers the chance to shape future MRAM memory interfaces while driving timing closure, power optimization, and
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
To View & Apply for jobs on this site that accept applications from your location or country, tap the button below to make a Search.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
Search for further Jobs Here:
×