Senior​/Principal Memory Circuit Design Engineer

Our client is an innovative semiconductor company developing next-generation memory products for mission‑critical computing, AI, industrial, aerospace, defense, and other high‑reliability applications where performance and data integrity are paramount.

They are seeking a Senior or Principal Memory Circuit Design Engineer to lead the architecture, design, optimization, and implementation of high‑speed DDR4/DDR5 interface circuitry for next‑generation MRAM products. This is an important role reporting to the VP of Engineering and offers the opportunity to help define the future of high‑performance non‑volatile memory.

• Architect, design, implement, and optimize high‑speed DDR4/DDR5 interface circuitry for advanced MRAM products, including DDR PHY integration, controller interface circuitry, timing‑critical paths, and high‑speed datapaths.
• Perform transistor‑level and mixed‑signal circuit design, simulation, analysis, debugging, and design verification.
• Drive timing closure, signal integrity, power optimization, and overall interface performance.
• Collaborate with architecture, memory, verification, and product engineering teams to integrate licensed DDR I/O IP into complete memory subsystems.
• Analyze silicon behavior, correlate simulation results with hardware performance, and drive design improvements.
• Participate in circuit design reviews and develop design specifications, implementation recommendations, and technical documentation.
• Provide technical leadership on future DDR interface architectures supporting higher data rates and next‑generation MRAM products.

• M.S. or Ph.D. in Electrical Engineering or a related discipline (B.S. with significant relevant experience will also be considered).
• Minimum 3–5 years and up to 20+ years of high‑speed circuit design experience in the semiconductor industry; role will be leveled Senior or Principal based on experience.
• Strong experience designing DDR4/DDR5 or memory interface circuitry (PHY, controller interface, or high‑speed datapath).
• Hands‑on experience with high‑speed digital and mixed‑signal circuit design, including transistor‑level simulation, debugging, and verification.
• Strong understanding of timing closure, signal integrity, high‑speed I/O design, and power optimization.
• Ability to collaborate effectively with architecture, verification, layout, and product engineering teams throughout the development cycle.

• Experience with memory products such as DRAM, LPDDR, HBM, SRAM, MRAM, NAND, or other high‑speed memory technologies.
• Experience integrating licensed DDR PHY or I/O IP into larger memory subsystems.
• Familiarity with memory controller architecture and high‑speed interface design.
• Experience optimizing high‑speed interfaces for improved bandwidth, timing margins, and power efficiency.
• Familiarity with MRAM or other emerging non‑volatile memory technologies.
• Experience with silicon bring‑up and post‑silicon debugging of high‑speed interfaces.
• Experience mentoring engineers or providing technical leadership on complex design projects.

• $200K–$275K base salary (depending on experience).
• 4 weeks of PTO annually.
• Stock options.
• Comprehensive Medical, Dental, Vision, and Life Insurance.
• 401(k).
• Relocation assistance may be available for an exceptional candidate.