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Formal Verification Engineer
Job in
San Francisco, San Francisco County, California, 94199, USA
Listed on 2026-07-27
Listing for:
Mirafra Technologies
Full Time
position Listed on 2026-07-27
Job specializations:
-
Engineering
Test Engineer, Hardware Engineer
Job Description & How to Apply Below
- Develop and execute formal verification plans for ASIC/SoC designs.
- Write System Verilog Assertions (SVA) and perform property, equivalence (LEC), and connectivity checking.
- Debug formal verification failures and collaborate with RTL/DV teams.
- Drive verification closure using industry-standard formal tools.
Requirements:
- 5+ years of ASIC/SoC verification experience.
- Strong expertise in Formal Verification, SVA, RTL (Verilog/System Verilog), and Assertion-Based Verification (ABV).
- Hands-on experience with Cadence Jasper Gold, Synopsys VC Formal/Formality, or Siemens Questa Formal.
- Knowledge of AMBA protocols (AXI/AHB/APB) and scripting (Python/Perl/Tcl) is a plus.
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