DFT Engineer – Post-Silicon Validation & Pattern Debug (Siemens Tools
Job in
San Francisco, San Francisco County, California, 94110, USA
Listed on 2026-08-05
Listing for:
ACL Digital
Full Time
position Listed on 2026-08-05
Job specializations:
-
Engineering
Test Engineer, Quality Engineering, Hardware Engineer, Validation Engineer
Job Description & How to Apply Below
Job Title
Own post-silicon structural test pattern debug and regeneration, including ATPG, MBIST, Boundary Scan, and related DFT flows
Analyze pattern failures on silicon and drive corrective actions in collaboration with tester teams
Utilize Siemens DFT/ATPG tools to modify, validate, and re-release production-ready test patterns
Correlate tester results with design intent to isolate coverage gaps and failure mechanisms
Drive closure of post-silicon DFT issues to improve yield and test robustness
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