Senior Physical Design (PNR) Engineer
Job in
San Francisco, San Francisco County, California, 94199, USA
Listed on 2026-08-09
Listing for:
Eximietas Design
Full Time
position Listed on 2026-08-09
Job specializations:
-
Engineering
Hardware Engineer, Systems Engineer, Electrical Engineering, Electronics Engineer
Job Description & How to Apply Below
Senior Physical Design (PNR) Engineer – Multiple Roles Locations:
San Jose or San Diego preferred (other locations can be discussed)
Experience:
10+ years Type:
Full-Time
Eximietas Design is expanding its Physical Design team and hiring Senior PNR Engineers to support advanced-node (5nm/3nm) semiconductor programs. We are looking for engineers who bring strong technical ownership in Floor planning, Top-Level Integration, or Block-Level PNR Implementation.
If you thrive on solving complex physical design challenges and want to help drive next-generation SoC designs, we want to talk to you.
Open PositionsWe are hiring across three specialisation areas within Physical Design:
What You Will Do Floor planning- Develop efficient, congestion-aware floor plans for blocks and top-level So Cs
- Own macro placement, pin assignment, and power grid planning
- Drive early feasibility for timing, IR, density, and overall PPA targets
- Lead top-level routing and physical integration across hierarchical designs
- Identify and resolve congestion, routing issues, and signoff-driven ECOs
- Ensure alignment and consistency across block owners and timing/signoff teams
- Achieve clean timing, DRC, and power results across MCMM scenarios
- Implement ECOs to optimise PPA and accelerate convergence at advanced nodes
- 10+ years of hands-on Physical Design / PNR experience
- Strong proficiency with Cadence Innovus (required); exposure to Tempus/Voltus is a plus
- Familiarity with Synopsys ICC2 or Fusion Compiler (preferred but not mandatory)
- Deep understanding of advanced-node challenges (MCMM, OCV, SI, IR, EM, density)
- Strong scripting skills (Tcl, Python, Shell) for flow automation and debugging
- Ability to collaborate effectively across RTL, Architecture, Verification, and Signoff teams
- Experience working on 7nm / 5nm / 3nm nodes is a strong advantage
- Work on cutting-edge advanced-node semiconductor programs
- High-impact roles with strong technical ownership
- A collaborative, engineering-centric culture
- Competitive compensation and growth opportunities
Position Requirements
10+ Years
work experience
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