Digital Microarchitect

# Digital Microarchitect Snowcap's chip architecture is being written for a logic family that has never shipped  will be the engineer who turns that architecture into microarchitecture an RTL team can actually code against — pipelines, datapaths, control, timing budgets, and the spec everyone implements from.

Team Chip Architecture Employment Full -time

Posted

May 2026

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01

About the Role Snowcap's top-level architecture defines what the chip does. RTL defines what gets built. The microarchitecture is the contract between them — and on a superconducting PCL digital chip, that contract cannot be copy-pasted from any prior program. The pipelines, datapaths, control logic, and timing budgets all have to be redrawn against a logic family whose clocking, energy, and signaling rules are not CMOS.

This role owns that translation.  You will take the architecture specification and produce the microarchitecture documents the RTL design team executes against. You will work directly with the Digital Architect on one side and RTL design and verification engineers on the other, in a flat, matrixed organization. You will operate fluently at both abstractions — pushing back on the architecture when the implementation will not hold, and pushing back on RTL when the spec is being interpreted past its intent.  

In twelve months, the microarchitecture documents you produce should be the artifact every RTL coder, verification engineer, and physical design lead points to when there is a question about how a block is supposed to work. Clean enough to implement from. Detailed enough to verify against. Defensible against physics and timing on the way down.
02

What You'll Own
- Translate top-level architecture specifications into detailed microarchitecture documents that RTL design engineers can implement directly, without guessing intent.  - Define pipeline stages, datapath structures, control logic, and timing budgets for each block you spec — including the parts where PCL timing assumptions diverge from CMOS.  - Own the microarchitecture-to-RTL handoff: defend the spec under review, answer implementation questions in real time, and revise the spec when implementation surfaces something the architecture missed.  

- Partner with the Digital Architect to flag micro-level issues back up the stack — the architectural choices that look fine on a system diagram and break at the pipeline level.  - Work directly with RTL design engineers and design verification engineers to ensure microarchitecture intent lands intact in the implementation and the testbench.  - Optionally own or co-own design verification for the blocks you specify — unit tests, architectural validation code, and the checks that prove the implementation matches intent.  

- Set the standard for what a microarchitecture document at Snowcap looks like — unambiguous, complete, and reviewable by both the architecture side and the implementation side.
03

What We Need to See
- Track record of microarchitecture definition on production silicon — chips that taped out, came back, and ran the workload they were designed for. Research-chip-only experience does not meet this bar.  - Demonstrated ability to write clear, unambiguous microarchitecture specifications that RTL engineers can execute against without follow-up clarification rounds.  - Solid working knowledge of the full RTL-to-GDS flow — synthesis, place and route, STA, and back-end realities — and the judgment to design microarchitecture that survives the trip downstream.  

- Fluency operating at both abstractions: architecture conversations with the architect, and RTL/implementation conversations with the design team, in the same week, often the same day.  - Comfort writing unit…