PD - IP Lead – Sr , Physical Design

Join the leading chiplet startup! As an Eliyan Sr Staff / Principal Physical Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross-functional team of industry experts that operate from first principles, innovate, and push the envelope to create high-volume and high-performance manufacturable products.

In this role, you will oversee and optimize the entire design flow, including synthesis, place-and-route (PNR), static timing analysis (STA), electromigration/IR drop analysis (EM/IR), and physical verification (PV – DRC, LVS, Antenna). You will also focus on developing and improving design flows and methodologies to ensure high-quality, on-time delivery. We offer a fun work environment with excellent benefits.

• Define and execute IP block and partition physical design strategy across projects, aligning schedules, resources, and milestones to company tapeout goals.
• Lead mixed signal placement and routing, enforcing analog keepouts, shielding, and DRC aware methodologies while integrating digital logic cleanly.
• Own system and block integration for floor planning, power, placement, CTS, and constraints, ensuring consistent interfaces across hierarchy and reuse.
• Drive end to end IP physical implementation from RTL handoff through GDSII, managing iterations, ECOs, and closure plans across corners.
• Develop and maintain block specific flow customizations for synthesis, PNR, EM IR, STA, and physical verification to improve QoR and predictability.
• Deliver robust constraints methodology, pushing timing intent from system to block and back, maintaining mode and corner correctness for signoff.
• Run and close subsystem signoff including STA, EM IR, SI, DRC, LVS, antenna, and metal fill, meeting reliability and manufacturability requirements.
• Optimize clock architecture and CTS for skew, latency, and power, including skew group definitions and balancing across library corners.
• Collaborate with front end, DFT, packaging, and manufacturing to resolve integration risks, test mode impacts, and physical interface requirements.
• Provide clear status, risk, and mitigation reporting to leadership, using metrics driven dashboards for PPA, convergence, and schedule predictability.

• Expertise in physical design, timing closure, and signoff for small to large ASIC IP blocks, including mixed signal integration and subsystem closure ownership.
• Strong hands-on experience with floor planning, power planning, placement, CTS, routing, EM IR, STA, and PV signoff across MMMC scenarios.
• Proven ability to improve flows through automation and scripting, with disciplined debug skills and data driven QoR and runtime optimization mindset.
• Excellent cross functional leadership and communication skills to drive alignment, technical reviews, and closure decisions under aggressive timelines.