VP, Physical Design & Chiplet Architecture
Listed on 2026-10-07
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Design & Architecture
Astera Labs seeks a VP of Physical Design to lead full-chip physical design for next-generation switching products with UCIe and UALink. You will drive multi-die architectures, tapeouts, and performance targets in collaboration with architecture, digital design, packaging, and silicon teams.
You will mentor a growing PD team, ensure robust timing closure, power and area optimization, and lead efforts across 7nm or below node implementations.
We invite applications for the VP, Physical Design & Chiplet Architecture position located in San Jose, CA, United States.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the VP, Physical Design & Chiplet Architecture role in the description above.
We appreciate your interest in this position.
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