Senior Engineer, RTL Memory Centric Computing

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Advancing the World's Technology Together Our technology solutions power the tools you use every day—including smartphones, electric vehicles, hyperscale data centres, IoT devices, and so much more. Here you will have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.

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The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system‑level challenges posed by the growing demands of future AI/ML workloads. Our team designs and develops scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimising energy consumption and maximising performance. To achieve this goal we collaborate closely with both hardware and software engineers to address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that provide a better balance between the hardware and software components of our systems.

We also conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionise how AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner.

Join us in shaping the future of computing!

We are looking for a Senior Engineer, RTL Memory Centric Computing. This role is being offered under the AGICL lab as part of DSRA. We are a research‑driven systems lab working at the intersection of large language models, accelerator hardware, and high‑performance software stacks. Our mission is to design, prototype, and optimise next‑generation AI systems through tight hardware‑software co‑design.

Location: Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

• Develop IP for memory‑centric computing systems using Verilog, System Verilog and HLS.
• Optimize the IP for performance, power and area by leveraging advanced design techniques such as pipelining, parallelism and data compression.
• Collaborate with Verification engineers to design and develop test plans.
• Make design decisions out of a large design trade‑off space across performance, power, thermal and cost.
• Troubleshoot and debug hardware issues and ensure the quality of the design through verification and validation.
• Stay up-to-date with the latest advancements in machine learning and hardware architecture and contribute to the development of new technologies.
• Communicate effectively with stakeholders, including users, partners and management, to ensure that the systems are delivered on time and within budget.
• Complete other responsibilities as assigned.

• Bachelor’s with 5+ years, or Master’s with 3+ years, or PhD with 0+ years of industry experience.
• Strong background in micro‑architecture and computer architecture.
• 5+ years of experience in front‑end design methodology involving RTL development for complex control and data‑path IPs.
• Experience in designing Memory Controller, NOC, Interconnect IP.
• Experience in Memory‑Centric computing IP and SOC integration.
• Experience in AI/ML workloads.
• Strong analytical and problem‑solving skills.
• Excellent communication and interpersonal skills.
• Ability to work independently and as part of a team.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building…