CMOS Interconnect Engineer; Foundry-Focused BEOL Technologies
Listed on 2026-02-06
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Engineering
Electrical Engineering
Destination 2D is Hiring: CMOS Interconnect Engineer (Foundry-Focused BEOL Technologies)
Destination 2D is pioneering the introduction of
intercalated-graphene interconnectsinto mainstream CMOS — a breakthrough now featured in leading industry roadmaps. We’re seeking aCMOS Interconnect Engineer with deepfoundry and BEOL process expertise to help mature and qualify next-generation graphene interconnect technologies for industry adoption.
This is a hands-on engineering role for a seasoned interconnect specialist with
7+ yearsof direct industry experience, ideally from leading foundry or IDM environments. You’ll work at the intersection of design, fabrication, and reliability — executing wafer-scale experiments and driving data-backed optimization toward foundry-qualified BEOL flows.
- Design and optimize BEOL interconnect and test structures within foundry design and reliability rules.
- Develop, fabricate, and characterize electrical and reliability test vehicles (via chains, line/via resistance, EM, SM, TDDB, and leakage structures).
- Perform fine-pitch interconnect fabrication (sub-10nm linewidths) and adhesion testing.
- Contribute to metallization, low‑k dielectric integration, and BEOL process development.
- Analyze electrical, structural, and reliability data to guide optimization.
- Support evaluation and integration of graphene-based interconnects, including test structure design and electrical testing.
- Collaborate with internal teams and external foundry partners to support process qualification and technology transfer.
- Masters or Ph.D. in Electrical Engineering, Materials Science, or a related field.
- 7+ years of hands-on industry experience in CMOS interconnects (design, fabrication, reliability) within foundry or IDM settings.
- Expertise in BEOL process integration, metallization, and low‑k dielectric technologies.
- Proven record of delivering interconnect technologies at scale (design rules, PDKs, qualification).
- Hands-on experience with Cu, Ru, or other advanced interconnect materials; graphene knowledge is a plus.
- Strong execution focus and attention to detail in a fast-paced, startup environment.
Location:
San Jose, CA
- To Apply:
Send your resume toinfoand join us in shaping the future of semiconductor technology — where atomically thin materials meet foundry‑scale manufacturing.
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