Principal IC Digital Implementation AE
Listed on 2026-02-14
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Engineering
Systems Engineer, Electrical Engineering -
IT/Tech
Systems Engineer, Electrical Engineering
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
As an expert Digital Implementation and Signoff Field Applications Engineering (AE), you will work side-by-side with our leading edge customers. With your expertise, you ll help them deploy Cadence’s market-leading technologies in Synthesis, P&R, and Signoff to meet/exceed their PPA targets, achieve faster design closure, and turn their design concepts into reality. You will also work directly with the Cadence R&D group to drive customer requirements and influence the direction of Cadence next-generation products and technologies.
At Cadence, customers are at the heart of everything we do. Talented leaders like you enable us to materialize this passion into results. By working directly with Cadence R&D and driving customer engagements, you will enhance your in-depth knowledge in nanometer design, unlock unique expertise in digital design implementation, and level up your communication, customer, and sales skills.
ResponsibilitiesBe part of team of Application Engineers providing technical support to Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and timing/power signoff
Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules
Collaborate with team to conduct technical presentations and product demonstrations
Drive technical evaluations/benchmarks to success
Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements
Drive adoption and proliferation of Cadence tools and technologies
Provide guidance to the team to amend & augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows
Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements
Minimum
10+ years of industry Physical Design experience
BS degree Computer Science/Engineering, Electrical, Engineering, or related field
Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required
Prior experience with IC digital implementation flows and backend EDA tools including Place and Route, IR Drop, backend design timing and power closure
Experience with advanced nodes 10nm and below
Experience in scripting languages such as Tcl/Perl/Python is a must
Strong customer-facing communication and problem-solving skills
Strong personal drive for continuous learning and expanding professional skill sets
Strong verbal, written, and customer communication skills
MS degree Computer Science/Engineering, Electrical, Engineering, or related field
Prior experience with IC digital implementation flows and front-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking
Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus or ICC, ICC2, DC or Primetime is highly desired
Experience with advanced nodes 5nm and below
The annual salary range for California is $123,200 to $228,800. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.
Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
Equal Employment Opportunity Policy:
Cadence is committed to equal employment opportunity throughout all levels of the organization.
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