Lead Mixed Signal Design Verification Engineer

Lead Mixed Signal Design Verification Engineer page is loaded## Lead Mixed Signal Design Verification Engineer locations:
CARY:
SAN JOSE:
AUSTIN time type:
Full time posted on:
Posted Yesterday job requisition :
R53206##
** At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
** At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The Lead Mixed-Signal Verification Engineer is responsible for defining mixed-signal verification plans, models, and roadmaps and delivering complete Mixed-Signal DV solutions that address challenges across the full spectrum of diverse mixed-signal products. This also includes driving innovation across the Mixed-Signal verification flow to create efficient and accurate mixed-signal methodologies. The ideal candidate is expected to be a mixed-signal DV expert and the hub between all engineering teams.

Duties:
* Architect, develop, champion, and implement metric-driven mixed-signal verification solutions, in the areas of:
Digital/DMS/AMS testbench creation and generation  + Automatic Model generation and testing  + Cadence Design Systems AMS simulation flows  + Mixed-Signal Assertions and Checkers  + Behavioral Modeling and Model Validation Methodologies  + Mixed-Signal VIP integration and testing  + Mixed-Signal emulation flows and practices
* Power intent verification including Low power states, state retention, and CPF/UPF integration
* Push technology for mixed-signal modeling, simulation, and DV in order to improve mixed-signal verification efficiency and accuracy.
* Ensure scalable mixed-signal DV solutions to cover the breadth of IPG offerings including Ser Des, DDR, A2D converters, and custom solutions
* Drive adoption of analog behavioral modeling methodologies for efficient mixed-signal verification
* Develop efficient debug solutions and techniques
* Develop an efficient and accurate full-stack mixed-signal methodology for the entire IP stack from the controller to the analog circuit.
* Propagate mixed-signal knowledge and mentor junior engineers
* Collaborate closely with:  + Digital, Analog, Firmware, and Test engineers  + Internal methodology and tool development teams, such as Virtuoso/ADE/Xcelium. PDK teams  + Customer management and engineering support teams
** Qualifications
* ** 4+ Years’ experience in working with Digital and Analog mixed-signal environments and teams.
* Must have good written and verbal cross-functional communication skills.
* Proven experience in most of the following:
* Creating Verification infrastructure (test-bench, environment, scripting)
* Scripting of verification flows, design automation
* Debugging verification test cases
* Knowledge of existing and upcoming standards such as PCIE, USB, DDR4, etc.
* Must be comfortable interacting across the IPG development team including the ability to understand design constraints.
* Knowledge of multiple programming languages. C++, Python, System Verilog, and e (verification language) are a plus
* Knowledge of Mixed-Signal Cadence tools and mixed-signal methodology is a plus
* Knowledge of System Verilog and UVM Test environment and methods is a plus
* Working knowledge of revision control tools such as SOS, SVN is a plus
* ** Education Level**:
Bachelor's Degree (MSEE/PhD Preferred)#LI-MA1##
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** Cadence is committed to equal employment opportunity throughout all levels of the organization.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to…