ASIC​/SoC Design Engineer, RTL design SoC IPs

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Join AMD’s Silicon Design team to design and develop cutting‑edge IPs for next‑generation embedded products. As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro‑architecture specification through production silicon, working on complex IP design.

The ideal candidate is a seasoned ASIC/SOC designer with proven expertise across the entire chip development lifecycle—from RTL design through silicon bring‑up. You excel in Verilog RTL coding, timing closure, and physical design awareness. With multiple production tape‑outs under your belt, you bring deep technical expertise, strong ownership, and the ability to mentor junior engineers while driving projects to successful completion.

• RTL Design & Microarchitecture: Author detailed micro‑architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets and timing requirements.
• Full ASIC Development Lifecycle: Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post‑silicon validation.
• Timing Closure & Optimization: Develop and maintain timing constraints (SDC), perform static timing analysis (STA) using industry‑standard tools (Prime Time/Tempus), resolve timing violations, and collaborate with physical design to achieve timing closure.
• SOC Integration: Integrate complex ASIC IP blocks into full‑chip SOC environment, ensuring proper connectivity, clock domain crossings, and interface compliance with industry‑standard protocols (AMBA AXI/AHB/APB, PCIe, CXL).
• Design Quality & Verification: Partner with verification teams to ensure comprehensive functional coverage; implement design‑for‑test (DFT) and design‑for‑debug (DFD) features; participate in RTL quality reviews and signoff.
• Physical Design
  
  Collaboration:
  
  Work closely with physical design engineers on floor planning, placement constraints, clock tree synthesis, and power grid design to ensure timing convergence and manufacturing readiness.
• Automation & Productivity: Develop Python/Perl/Tcl scripts to automate repetitive tasks, improve design quality checks, and enhance team efficiency throughout the design flow.
• Cross‑Functional
  
  Collaboration:
  
  Engage with architecture, verification, physical design, CAD, and post‑silicon teams to resolve complex technical challenges and deliver high‑quality silicon on schedule.

• Proven track record with 2+ production ASIC tape‑outs in senior design roles
• Expert‑level Verilog RTL coding skills with deep understanding of synthesizable RTL constructs and coding best practices
• Hands‑on experience with the complete ASIC design flow: RTL, synthesis, STA, physical design, tape‑out
• Experience writing and debugging SDC timing constraints, including multi‑cycle paths, false paths, and clock domain crossing constraints
• Experience integrating complex IP blocks into SOC designs
• Knowledge of industry‑standard on‑chip interconnect protocols (AMBA AXI/AHB/APB)
• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering

• Knowledge of ARM architecture and AMBA protocol specifications
• Familiarity with PCIe or CXL transaction layer protocols
• Experience with low‑power design techniques (clock…