Physical Design Engineer ASIC SoC in San Jose CA

Join a leading custom ASIC and System-on-Chip (SoC) development company delivering high-performance silicon solutions across emerging technologies. As a hands‑on Physical Design Engineer
, you’ll own projects from feasibility through tape‑out, collaborating with customers, frontend, and integration teams to ensure successful silicon delivery. Your expertise will directly impact complex 28nm and 16nm SoC programs.

• Competitive base salary ($170K–$220K) plus bonus

• Great benefits and exceptional 401(k)

• Full project lifecycle ownership — from inception to tape‑out

• Small, high‑impact teams where engineers are true contributors

• Exposure to advanced custom ASIC and SoC technologies

• Drive pre‑layout STA for feasibility analysis and timing constraint validation

• Lead chip‑ and block‑level floor planning and pin assignment

• Review clock specifications and execute clock tree synthesis (CTS)

• Perform placement, routing, and timing optimization

• Execute sign‑off activities including RC extraction, STA, IR‑drop analysis, and physical verification

• Debug physical verification (PV) issues and resolve sign‑off challenges

• Present technical updates in customer meetings and cross‑functional reviews

• Own physical design and synthesis end‑to‑end across multiple tape‑outs

• BSEE with 5+ years of experience (MSEE preferred)

• 10+ years of hands‑on experience in ASIC physical design and SoC development

• Proven track record of multiple successful tape‑outs from inception

• Strong experience at 28nm / 16nm process nodes

• Proficiency with ICC2 or Innovus

• Scripting expertise in Perl, Tcl, or Python

• Experience with
  Prime Time, Prime Power, Red Hawk
  , and physical verification tools

• Solid understanding of frontend design and hierarchical layouts

• Strong communication and problem‑solving skills

• Experience in small company environments preferred

• Local candidates preferred

Located in the heart of Silicon Valley, San Jose offers direct access to a world‑class semiconductor ecosystem and leading technology companies. The region combines a strong engineering community with year‑round California sunshine and easy access to both the coast and the mountains — making it an ideal base for hardware professionals building next‑generation silicon.

If you’re a seasoned Physical Design Engineer who thrives on full‑chip ownership and delivering successful tape‑outs, this is your opportunity to work on cutting‑edge SoC programs with meaningful impact. Apply today and help shape the next generation of custom silicon innovation.

$220,000 per year