Package Design Engineer

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Package Design Engineer

Associate III – Product Design

We are seeking a highly skilled Package Design Engineer with 5–8 years of experience in advanced IC packaging. The ideal candidate will have strong expertise in Flip Chip and multi‑layer (8+ layers) substrate design, with a solid understanding of substrate manufacturing and assembly rules. The role requires close collaboration with cross‑functional teams and vendors to deliver high‑performance, reliable, and manufacturable package solutions.

• Perform the design and development of multi‑layer package substrates (8+ layers) for advanced semiconductor devices.
• Perform package layout, routing, and stack‑up planning using EDA tools (Mentor Graphics, Cadence Allegro, PLA).
• Ensure designs comply with substrate manufacturing rules (trace width/spacing, via design, impedance requirements).
• Incorporate assembly rules (die placement, bump/ball pitch, solder joint reliability, warpage control) into package designs.
• Develop and validate Flip Chip package designs, including bump assignment, redistribution layers (RDL), and underfill considerations.
• Collaborate with Signal Integrity (SI), Power Integrity (PI), and thermal analysis teams to ensure robust performance.
• Partner with substrate vendors and OSATs to verify design manufacturability, yield, and assembly feasibility.
• Provide on‑site vendor support when required to resolve design and assembly issues.

This position description identifies the responsibilities and tasks typically associated with the performance of the position. Other relevant essential functions may be required.

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Materials Science, or related field.
• 5–8 years of hands‑on experience in package design, with proven expertise in multi‑layer (8+) substrate design.
• Proficiency with EDA tools:
  Mentor Graphics, Cadence Allegro, PLA (Mentor Graphics Xpedition / Cadence Allegro Package Designer).
• Strong knowledge of substrate manufacturing rules and assembly rules.
• Experience with Flip Chip package design methodologies.
• Familiarity with SI/PI/thermal considerations in advanced packages.
• Strong communication and collaboration skills for cross‑functional and vendor engagement.
• Flexibility to travel and provide on‑site vendor support as needed.

Compensation can differ depending on factors including but not limited to the specific office location, role, skill set, education, and level of experience. UST provides a reasonable range of compensation for roles that may be hired in various U.S. markets as set forth below.

California

$73,000–$110,000

Full‑time regular employees accrue a minimum of 10 days of paid vacation per year, receive 6 days of paid sick leave each year (pro‑rated for new hires), 10 paid holidays, and are eligible for paid bereavement leave and jury duty. They are eligible to participate in the Company’s 401(k) Retirement Plan with employer matching. They and their dependents residing in the U.S. are eligible for medical, dental, and vision insurance, as well as the following company‑paid employee‑only benefits: basic life insurance, accidental death and disability insurance, and short‑ and long‑term disability benefits.

Regular employees may purchase additional voluntary short‑term disability benefits and participate in a Health Savings Account (HSA) as well as a Flexible Spending Account (FSA) for healthcare, dependent child care, and/or commuting expenses as allowable under IRS guidelines. Benefits offerings vary in Puerto Rico.

Part‑time employees receive 6 days of paid sick leave each year (pro‑rated for new hires) and are eligible to participate in the Company’s 401(k) Retirement Plan with employer matching.

Full‑time temporary employees receive 6 days of paid sick leave each year (pro‑rated for new hires) and are…