Sr. Design Verification Engineer

Overview

Prodapt is a global technology company and the largest specialized player in the Connectedness industry. As an AI-first strategic partner, Prodapt provides consulting, business transformation, and managed services to top telecom and tech enterprises. Prodapt ASIC Services is a leading provider of SoC ASIC/FPGA and Embedded Software services. We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas such as RTL Design,
UVM Verification
, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services include firmware, device drivers, RTOS porting, and board bring-up. A “Great Place To Work® Certified™” company, Prodapt employs over 6,000 technology and domain experts in 30+ countries. Prodapt is part of the 130-year-old business conglomerate The Jhaver Group, which employs over 32,000 people across 80+ locations globally.

Sunnyvale, CA or Austin, TX

2 year Project

• Collaborate with cross-functional teams to ensure the effective verification of complex SoC designs.
• UVM Expertise
• Develop and maintain scripts using languages such as Perl, Python, Unix shells, and Makefiles to automate testing and verification processes.
• Gain an in-depth understanding of high-speed interfaces, including PCIe, USB, NOC, NVMe, Ethernet, LPDDR5, and HBM2, to ensure seamless integration into complex SoC designs.
• Collaborate with lab managers to set up and manage the necessary infrastructure for emulation and verification activities.
• Contribute to the development of comprehensive verification plans, test benches, and methodologies.
• Identify and propose improvements to streamline the emulation and verification process.

• Bachelor's or higher degree in Electrical Engineering, Computer Science, or a related field and 8+ years of System Verilog/UVM experience (IP, sub-system, or SoC level verification).
• Strong scripting skills (Python, TCL, Perl, Shell) for automation and tool development.
• EDA tool expertise (VCS, Xcelium, Questa, Verdi, Spyglass, etc.).
• Experience in debugging, root‑cause analysis, and driving verification closure.
• Familiarity with CPU/GPU verification, AI/ML, Networking, or micro‑architectural performance verification is a plus.
• High‑speed interface verification (PCIe, DDR, HBM, Ethernet, RoCE) preferred.