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Senior ASIC​/RTL Design Engineer - SoC Timing & Automation

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: AMD
Full Time position
Listed on 2026-02-21
Job specializations:
  • Engineering
    Systems Engineer, Electrical Engineering, Electronics Engineer, Engineering Design & Technologists
Salary/Wage Range or Industry Benchmark: 100000 - 125000 USD Yearly USD 100000.00 125000.00 YEAR
Job Description & How to Apply Below
A leading semiconductor company is seeking a Senior ASIC/RTL Design Engineer in San Jose, California. The role involves designing and integrating complex SoCs, focusing on RTL ownership, timing constraints, and debugging SDC development. Ideal candidates possess strong collaborative skills, advanced EDA tool knowledge, and TCL scripting capabilities. A Bachelor's or Master's degree in Electrical or Computer Engineering is required. This position does not support visa sponsorship.
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Position Requirements
10+ Years work experience
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