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ASIC Design Engineer — Co-Packaged Optics; On-Site SJ
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-02-21
Listing for:
Ayar Labs
Full Time
position Listed on 2026-02-21
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Hardware Engineer, Engineering Design & Technologists
Job Description & How to Apply Below
A cutting-edge technology company based in San Jose is seeking an ASIC Engineer to design complex systems-on-chip (SoCs). The role involves optimizing RTL designs, developing verification methodologies, and debugging custom silicon. Ideal candidates should have a degree in Electrical or Computer Engineering and at least 1 year of ASIC design experience. Proficiency in Verilog and ASIC verification tools is essential.
Competitive salary ranging from $130,000 to $150,000.
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