IP Design Engineer

Overview

WHAT YOU DO AT AMD CHANGES EVERYTHING. At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers to PCs, gaming and embedded systems. We push the limits of innovation to solve the world’s most important challenges with execution excellence, collaboration, and inclusivity. Join us as we shape the future of AI and beyond.

Together, we advance your career.

We are looking for a self-motivated senior design engineer to be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry-leading technologies to market. As a key contributor, you will focus on RTL design and validation of high-speed interfaces such as chip-to-chip interconnect, both on system and on package, and highly configurable multi-protocol PHYs.

Continuous technical innovation to increase productivity, to heighten quality of results, and to foster career development is integral to the role.

You demonstrate a strong passion for digital design, are a collaborative team player, and possess excellent analytical and problem-solving skills. You are eager to learn and take full ownership of challenges.

• Perform RTL design of the digital components.
• Experience with designing IPs for FPGAs (AMD/Altera).
• Good knowledge of FPGA tool chains (Vivado/Quartus).
• Develop and validate timing constraints involving multiple clock domains while working with physical design to harden IP.
• Help lead and mentor other engineers to achieve project goals and organizational growth.
• Work with a functional (design) verification team to meet coverage and quality standards.
• Analyze/fix Lint and CDC/RDC errors of the components.
• Guarantee quality/timely deliverables meeting project’s schedule.
• Help to improve and automate design process.
• Support post-silicon product bring-up/debug.

• Strong experience in designing digital components for high-performance, low-power SOC/FPGA.
• Design of digital circuits and components using Verilog/System Verilog.
• Creating and maintaining timing constraints for complex multi-clock designs.
• Debugging in digital and mixed-signal simulation environment.
• Power-optimization of digital designs.
• Multi-clock domain designs.
• Experience/Knowledge of DDR Memory Controllers and Calibration algorithms is a plus.
• Logic synthesis, timing closure, logical equivalence checking and ECOs.
• Scripting languages such as Perl, Tcl, or Python.
• Collaboration with verification team.
• Excellent verbal and interpersonal communication skills.
• Excellent technical communications. Ability to produce technical documentation.
• Exhibit strong ownership of tasks and responsibilities.

• Bachelors or Masters degree in Electrical Engineering with relevant industry experience

San Jose

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

AMD is an equal opportunity, inclusive employer. We consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under applicable laws during the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.

This posting is for an existing vacancy.