Manager, FPGA IP Design Engineering

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We are seeking a technically strong, execution‑driven engineering manager to lead end‑to‑end development of FPGA‑based IP—from concept through post‑silicon validation. This role will guide a high‑performing team of specialists to deliver optimized, customer‑ready IP solutions such as LPDDR5/6, DDR5/6, MIPI, Display port and HDMI.

You are a collaborative, detail‑oriented leader who thrives in fast‑paced, cross‑functional environments. You bring strong communication, problem‑solving ability, and an ownership mindset to drive complex product development. You possess deep technical expertise in FPGA‑based IP flows, RTL development, and validation methodologies, along with the leadership skills needed to motivate and guide teams across global sites.

• Define product requirements using input from engineering and marketing.
• Drive early‑phase cost modeling, resource planning, and schedule estimates.
• Align product roadmap and schedules with external partners and vendors.

• Collaborate with architecture and verification teams to balance timing, performance, and schedule trade‑offs.
• Support engineering execution from RTL development through FPGA timing closure.
• Lead cross‑functional alignment and resolve issues across the development lifecycle.
• Provide technical direction on IP selection, protocols, and System Verilog‑based design decisions.

• Ensure comprehensive test plans and validation strategies are completed before silicon bring‑up.
• Oversee characterization, validation, and silicon debug activities.
• Integrate feedback from marketing and technical marketing to ensure product‑to‑customer alignment.
• Identify validation gaps and drive cross‑team closure.

• Own the full solution lifecycle—from product definition to validated, customer‑deployable silicon.
• Ensure deliverables meet cost, performance, and time‑to‑market goals.
• Coordinate with hardware, software, and customer‑facing teams to enable complete solution readiness.

• Proven success delivering hardware products from concept to post‑silicon validation.
• Strong background in FPGA, IP, or ASIC design and verification flows.
• Experience with DDR, memory controllers, MIPI, or HDMI.
• Knowledge of memory technologies (DDR5/DDR4, LPDDR5/LPDDR6) and JEDEC standards.
• Hands‑on experience with System Verilog, digital design methodologies, and protocol integration.
• Familiarity with FPGA IP development flows and verification.
• Strong understanding of customer requirements, system‑level trade‑offs, and solution architecture.
• Demonstrated ability to excel in dynamic, cross‑disciplinary environments.
• Scripting and automation proficiency to enhance design and validation workflows.
• Experience working effectively across global teams.

• Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering.

• San Jose, CA

Role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.