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ASIC Design Engineer — RTL/Verilog EDA Platforms
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-02-28
Listing for:
Cadence Design Systems
Full Time
position Listed on 2026-02-28
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Hardware Engineer, Engineering Design & Technologists
Job Description & How to Apply Below
A leading global electronic design automation company seeks a Design Engineer in San Jose, California. The successful candidate will focus on designing and testing ASICs for cutting-edge chip emulation applications, employing advanced electronic theory. This role requires strong skills in RTL coding using Verilog/System Verilog and offers a salary range of $156,853 to $213,200, along with competitive benefits including a 401(k) plan and employee stock purchase plan.
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