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Senior ASIC Verification Engineer SystemVerilog UVM

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Broadcom
Full Time position
Listed on 2026-02-28
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Test Engineer, Engineering Design & Technologists
Salary/Wage Range or Industry Benchmark: 100000 - 125000 USD Yearly USD 100000.00 125000.00 YEAR
Job Description & How to Apply Below
A leading semiconductor company is looking for an ASIC verification engineer to join their high-performance design team in San Jose, California. The candidate will develop advanced verification environments and analyze simulation results. This role requires a Bachelor's degree in Electrical Engineering or Computer Science and over 12 years of experience in system and block level verification. Competency in System Verilog and UVM is essential, and experience with FPGA prototyping is a plus.

A comprehensive benefits package is offered.
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Position Requirements
10+ Years work experience
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