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Senior Memory IP Architect Perf IC Design
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-02-28
Listing for:
Cadence Design Systems, Inc.
Full Time
position Listed on 2026-02-28
Job specializations:
-
Engineering
Systems Engineer, Hardware Engineer, Electronics Engineer, Engineering Design & Technologists
Job Description & How to Apply Below
A leading electronic design automation company in California is seeking an experienced architect for memory IP who will be responsible for the design and ownership of high-performance memory IP architecture. The role requires a BS or MS degree in electrical engineering with several years of experience in logic design and a strong technical background in Verilog/System Verilog. Competitive compensation, including a salary range of $154,000 to $286,000, along with various benefits is offered.
Ideal candidates will possess excellent communication skills and a collaborative spirit.
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Position Requirements
10+ Years
work experience
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