Senior ASIC & SoC Verification Engineer
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-02-28
Listing for:
TetraMem - Accelerate The World
Full Time
position Listed on 2026-02-28
Job specializations:
-
Engineering
Systems Engineer, Test Engineer, Electronics Engineer, Engineering Design & Technologists
Job Description & How to Apply Below
Proficiency in UVM/OVM and Verilog is critical. Competitive salary range from $110,000 to $300,000 annually based on experience.
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Position Requirements
10+ Years
work experience
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