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Technology Development Engineer

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: Cisco Systems, Inc.
Full Time position
Listed on 2026-05-09
Job specializations:
  • Engineering
    Manufacturing Engineer, Packaging Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 USD Yearly USD 80000.00 100000.00 YEAR
Job Description & How to Apply Below
Position: Package Technology Development Engineer

Cisco is seeking a seasoned Packaging Technical Leader to join the Packaging Technology & Quality team within our world‑class Global Supply Chain. As a Technical Leader you will drive innovation in advanced packaging technology and quality for Cisco’s cutting‑edge ASIC and silicon photonic products.

Your Impact

You will operate at the intersection of advanced technology and strategic execution, working within a highly collaborative and multi‑functional environment. This includes close partnerships with design engineering, operations, and supply chain teams to innovate next‑generation technologies. You will also engage directly with counterparts at OSATs, Fabs, contract manufacturers and other key suppliers, leading technical discussions and problem‑solving efforts while influencing commodity strategy at a global scale.

Key Responsibilities
  • Serve as a technical leader in advanced packaging technology development (2.5D/3D, TSV, MCM, flip‑chip, heterogeneous integration). Oversee package assembly, process development, reliability qualification, materials, and testing.
  • Work with top‑tier package assembly partners to develop and qualify packaging solutions for Cisco products.
  • Drive/support quality initiatives such as failure analysis (FA), root cause finding, and implementation of corrective actions.
  • Work collaboratively with design teams to influence package architecture and provide expert guidance on Design for Manufacturability/Reliability (DfM, DfR), contributing to critical parameters for high‑volume manufacturing.
Minimum Qualifications
  • 7+ years of progressive industry experience in semiconductor packaging, photonic packaging, or assembly process development or integration, with a demonstrable track record of technical leadership and successful project execution.
  • Knowledge of advanced packaging processes (bumping, flip‑chip, TSV, 2.5D/3D, MCM) and materials.
  • Experience with package reliability & qualification, FMEA, structured problem‑solving methods such as 8D, and physical failure analysis techniques.
Preferred Qualifications
  • Familiarity with wafer‑ and package level‑test and debug as well as ATE platforms and test hardware.
  • Experience or familiarity with co‑packaged optics.
  • Experience with volume manufacturing.
  • Experience with advanced simulation tools for package design and reliability analysis.
  • Ability to work within and lead projects with highly multi‑functional and geographically distributed technical teams.
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