Senior Debug Verification Engineer

Overview

About Altera

At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

Sr. Debug Design Verification Engineer. You will be responsible for Design for Debug architecture verification related tasks including creating test cases and test benches using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable effective verification. Coordinate cross‑functional efforts with Design, SW, Architecture teams to achieve full coverage verification plan.

Use system full application to verify performance and identify shortfalls.

• Pre-silicon system verification, including SoC, FPGA & Full Chip design verification.
• Create test cases and test benches with UVM methodology.
• Full chip/system functional verification by defining verification strategies, methodology, and test plans to enable effective verification.
• Experience with Design for Debug (JTAG, High speed USB, PCIe based debug, Visualization of Internal Signal) architecture and design verification.
• Experience with ARM and RISC Debug Architectures is desired with focus on design verification.
• Prior experience with Ultra
  
  SoC/Tessent Embedded Analytics Debug Architecture is a plus but not required.
• Coordinate cross‑functional efforts with Design, SW, Architecture teams to achieve full coverage verification plan.
• Experience in Emulation is an add‑on.

• Minimum qualifications:
  
  8+ years of experience with complex ASIC designs and/or verification.
• 8+ years of experience with System Verilog language.
• 8+ years of experience with UVM verification methodology, and formal verification method.
• 8+ years of experience scripting in Linux/Unix environments; proficiency in Perl and/or Python is desirable.
• Strong communication skills and ability to work with a team across different geography sites.

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$149,100 - $215,000 USD

All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

About Altera

Altera:
Accelerating Innovators. Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, Smart

NICs and IPUs. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.

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