Low power Design Engineer

Overview

Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi-dimensional approach enables us to solve the most critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries.

Job Requirements

Position: Low Power Design Engineer

We are looking for humble geniuses who believe that engineering has the potential to make the impossible possible; innovators who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all.

If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we’re eager to hear from you.

Perform physical design of 2nm/3nm/5nm multi-GHz IP for network switch products. Be able to come up with floorplan, powerplan, CTS and routing of the design using state-of-the-art EDA tools like Innovus. Work closely with designers and must be able to write TCL script to perform custom/semi-custom standard cells placements/clock tree adjustments/routing to achieve design specs (STA/IR/EM/LVS/DRC). Good timing analysis and CTS knowledge is required.

This role requires a strong background in low power design implementation, with specific emphasis on using/developing UPF to drive power-aware signoff.

• Power Specification and UPF Development:
  Work with architects and logic designers to understand power requirements, define power specifications, and develop the Unified Power Format (UPF).
• Low Power Implementation:
  Use Design Compiler (DC) to perform low-power insertion, debug & identify issues with low power cells insertion, and update the UPF.
• Implement low power insertion techniques, including the automatic insertion of retention flops, isolation cells, and level shifters during synthesis (DC-VCLP flow), formal verification tools.
• Support UPF for design, DV, Synthesis, Formality, DFT and PNR teams.
• Verification and Sign-off (VCLP/Formal):
  Verify and sign-off the low power intent using low power checking tools such as VCLP or CLP.
• Debug and resolve UPF validation and low power rule violations, including issues related to retention, level shifters and isolation rules, and understand formal verification issues related to the low power intent.

• Hands-on experience in defining power intent using UPF.
• Proficiency in low power verification using VCLP/CLP.
• Expertise in synthesis with low power cell insertion (e.g., isolation, level shifters, retention) using tools like Design Compiler.

Pay Range: $150000 - $200000 per year

Compensation decisions are made based on factors including experience, skills, education, and other job-related factors, in accordance with our internal pay structure. We also offer a comprehensive benefits package, including health insurance, paid time off, and retirement plan.

This role is considered an on-site position located in San Jose, CA
.

• You must be able to commute to and from the location with your own transportation arrangements to meet the required working hours.