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Packaging Engineering Project Manager; Experienced Packaging Technologist

Job in San Jose, Santa Clara County, California, 95199, USA
Listing for: TSMC - Taiwan Semiconductor Manufacturing Company Limited
Full Time position
Listed on 2026-06-04
Job specializations:
  • Engineering
    Packaging Engineer, Product Engineer
Salary/Wage Range or Industry Benchmark: 125000 - 210000 USD Yearly USD 125000.00 210000.00 YEAR
Job Description & How to Apply Below
Position: Packaging Engineering Project Manager (Experienced Packaging Technologist)(7477)

Packaging Engineering Project Manager (Experienced Packaging Technologist)(7477) Overview of Role

We are seeking an enthusiastic and highly experienced professional in advanced semiconductor packaging technology to join our Field Technical Solutions team. This pivotal role involves dynamic collaboration with leading customers, our North American sales force, and our global engineering headquarters. Our mission is to empower customers to rapidly and efficiently design their next generation of 'must-have' products. This is achieved by deeply understanding their technical needs, then defining, promoting, and enabling the most competitive and innovative packaging solutions within our cutting-edge 3DFabric technology portfolio.

You will report to the Director of the Field Technical Solutions-Advanced Packaging Department. Currently, we are operating in a hybrid work schedule with four days in the office.

Responsibilities
  • Build relationships and trust with customers through technical interaction.
  • Own the technical solution for customers and champion their needs.
  • Justify the packaging business by understanding customers’ products, roadmaps, and technical needs in advanced packaging technologies.
  • Identify and drive internals teams to develop competitive and creative technical solutions.
  • Host the engagement meetings between customer and internal teams on engineering/technology discussions.
  • Provide local technical support together with sales team to customers as required.
  • Introduce/train customers on our 3DFabric technology to enable them to create world class products.
  • Ensure clear and accurate external and internal communication.
  • Be a technical expert in NA office in advanced packaging, supporting customer engagement and internal technology alignment.
  • Manage customer projects for advanced 2.5D/3D packaging, including those for leading AI/HPC applications, guiding them from conceptualization through production qualification.
  • Communicate with customers on package architecture and floor planning based on design rules and simulation/modeling (themo-mechanical and thermal simulation) outcomes for feasibility evaluation and floor plan optimization.
  • Direct substrate technology development, collaborating with external suppliers and internal teams to explore advanced materials (e.g., low Dk/Df ABF, low CTE) and multi-layer core schemes.
  • Conduct comprehensive research and competitive analysis of advanced 2D/3D packaging technologies across the global semiconductor industry to influence strategic direction.
  • Lead and coordinate cross-functional review meetings involving various stakeholders (e.g., design, quality, process development/integration, testing, product teams) for complex project development.
  • Coordinate HQ resources on failure analysis and root cause finding during package development phase in order to deliver customer products.
Minimum Qualifications
  • Master’s Degree, or above, in Mechanical Engineering, Materials Science/Engineering, Electrical Engineering, or Electro-Optical Engineering.
  • Proven, strong technical background with 12+ years of industry experience in advanced semiconductor packaging.
  • Extensive hands‑on experience with cutting‑edge advanced packaging technologies, such as:
  • 2.5D/3D Packaging (e.g., CoWoS, InFO, SoIC, or similar advanced wafer‑level integration schemes).
  • Bonding Technologies (e.g., Wafer‑on‑Wafer bonding, Chip‑on‑Wafer bonding) and assembly technologies (e.g. flip chip, reflow, TCB, etc.)
  • Heterogeneous Integration (e.g., 3

    DIC and other advanced heterogeneous packages) from concept/architecture to execution.
  • Specific areas of expertise such as photonic packaging (Si‑Photonic integration, Co‑Packaged Optics - CPO), thermal/thermos‑mechanical simulation/modeling are highly valued.
  • Demonstrated expertise in packaging process development, Wafer‑Level System Integration, and manufacturing capabilities expansion.
  • Profound knowledge of chip‑package interaction, assembly processes, thermo‑mechanical behavior of packages and their materials, and electrical performance requirements on packages.
  • Understanding of packaging design flow and concepts (including EDA tools), electrical functional tests, and…
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