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Senior Principal DSP & SerDes RTL Design Engineer
Job in
San Jose, Santa Clara County, California, 95199, USA
Listed on 2026-06-05
Listing for:
Cadence
Full Time
position Listed on 2026-06-05
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
Cadence in San Jose is looking for an engineer to develop high-speed PMA layer IP for industry-standard protocols. Candidates must have substantial experience with Verilog, proficient skills in RTL logic design, and strong digital microarchitecture knowledge. This role entails collaboration with cross-functional teams to enhance digital design and functional verification processes.
The position offers a competitive salary range of $154,000 to $286,000, with additional incentive compensation opportunities including bonuses and stock options. Join us in making impactful technological advancements.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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